Homepage
Hi! I am a sixth-year Ph.D. student in the Department of Electrical & Computer Engineering at The University of Texas at Austin. I work with Professor Mohit Tiwari in the SPARK Research Lab. My research interests lie in system and processor architecture security.
Previously I was an undergraduate research intern in the DASlab at Harvard SEAS, where I worked on workload-aware data partitioning supervised by Professor Stratos Idreos.
In 2016, I graduated with my bachelor degree from Chu Kochen Honors College, Zhejiang University in Computer Science.
You can find my cv here.
Research Interest
Computer Security spans across all layers of the computing stack. I am interested in bridging the gap between application-layer security requirements and low-level system and hardware primitives. Our work Cyclone enables software like browsers and Linux kernel to communicate fine-grained security domain information to hardware, allowing detection of hardware side-channels with a high true-positive rate and extremely rare false positives. In SESAME, we build a framework that enables software developers to tailor accelerator-TEEs to the minimal required threat models, enabling domain-specific optimizations to re-gain performance.
Recent Activity
Dec 2023 | Our work Tail Victims is accepted to SEED! |
Oct 2023 | I attended the ACE center Annual Review meeting at UIUC. Super thrilled to present our characterizations on the architectural and side-channel implications of security domains. |
Sept 2023 | Our work led by Sarbartha on programming accelerator enclaves with deployment-specific threat models is accepted to HASP [DOI]! Congratulations Sarbartha! |
Apr 2023 | I passed my qualifying exam and am now officially a doctoral candidate! |
Sept 2022 | Our proposal on securing many-domain processors was selected as a winner of the Qualcomm Innovation Fellowship (North America) 2022! |
Sept 2022 | Our work led by Yongye on an architecture-faithful metric for browser performance benchmarking is accepted to IEEE CAL [DOI]! Congratulations Yongye! Check out how the page-load-time metric might be lying about site power usage. |
June 2022 | I presented our work Cyclone at MSR Intern Security Workshop. Thank you to the participants for the insightful discussions! |
May 2022 | I started as a research intern at Azure Hardware Architecture (AHA). Super exited about confidential computing in the cloud and exploring what that means for hyervisor offloading! |
April 2022 | We were selected to Qualcomm Innovation Fellowship'22 Finalist! |
May 2020 | I started as a research intern at the SysML group of Facebook AI Research (FAIR). I am exploring and optimizing use cases of Intel SGX to protect user privacy in Facebook applications. |
Oct 2019 | My co-author Austin Harris presented our work Cyclone at MICRO'19. We had lots of deep-dvies of Cyclone and transient side-channel attacks at our poster. |
Sept 2019 | I presented Power-Anomalies, and my advisor Professor Mohit Tiwari presented our work Cyclone at the ARM Research Summit 2019. It was such a great time talking to all the researchers and making new friends at the Summit! |
Jul 2019 | Our work Cyclone is accepted to MICRO'19! |
Jun 2019 | I attended ISCA'19 (FCRC 2019) and helped organize the Side and Covert Channels Tutorial. It was great to be at FCRC, learned a lot from great presentations and insightful discussions! |
May 2019 | I presented our work "Using Power-Anomalies to Counter Evasive Micro-Architectural Attacks in Embedded Systems" in the IEEE International Symposium on Hardware Oriented Security and Trust (HOST'19). |
Jan 2019 | Power-Anomalies is accepted to HOST'19 and nominated for the Best Paper Award! |